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HD6417618 Datasheet(PDF) 635 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 635 Page - Renesas Technology Corp

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Rev. 6.00 Jun. 12, 2007 Page 603 of 610
REJ09B0131-0600
Item
Page Revision (See Manual for Details)
Figure 21.23 Synchronous
DRAM Burst Write Bus Cycle
(Single Write
× 4)
(Auto-Precharge, WTRCD = 1
Cycle, TRWL = 1 Cycle)
566
Amended
Tc2
Tc3
Tc4
Trwl
Tr
Tc1
Trw
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
CKIO
A25 to A0
Row
address
Column
address
Column
address
Column
address
Column
address
Figure 21.24 Synchronous
DRAM Burst Read Bus Cycle
(Single Read
× 4)
(Bank Active Mode: ACT + READ
Commands, CAS Latency = 2,
WTRCD = 0 Cycle)
567
Amended
Tc3
Tc4
Tde
Tr
Tc2
Td1
Td2
Td3
Td4
Tc1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
CKIO
A25 to A0
Row
address
Column
address
Column
address
Column
address
Column
address
Figure 21.25 Synchronous
DRAM Burst Read Bus Cycle
(Single Read
× 4)
(Bank Active Mode: READ
Command, Same Row Address,
CAS Latency = 2,
WTRCD = 0 Cycle)
568
Amended
Tc2
Tc4
Tde
Tc1
Tc3
Td1
Td2
Td3
Td4
tAD1
tAD1
tAD1
CKIO
A25 to A0
Column
address
Column
address
Column
address
Column
address
tAD1
tAD1
Figure 21.26 Synchronous
DRAM Burst Read Bus Cycle
(Single Read
× 4)
(Bank Active Mode: PRE + ACT +
READ Commands, Different Row
Addresses,
CAS Latency = 2, WTRCD = 0
Cycle)
569
Amended
Tc3
Tc4
Tde
Tc2
Td1
Td2
Td3
Td4
Tc1
Tr
Tpw
Tp
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
CKIO
A25 to A0
Column
address
Column
address
Column
address
Column
address
Row
address
Figure 21.27 Synchronous
DRAM Burst Write Bus Cycle
(Single Write
× 4)
(Bank Active Mode: ACT + WRITE
Commands, WTRCD = 0 Cycle,
TRWL = 0 Cycle)
570
Amended
Tc2
Tc3
Tc4
Tr
Tc1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
CKIO
A25 to A0
Row
address
Column
address
Column
address
Column
address
Column
address
Figure 21.28 Synchronous
DRAM Burst Write Bus Cycle
(Single Write
× 4)
(Bank Active Mode: WRITE
Command, Same Row Address,
WTRCD = 0 Cycle,
TRWL = 0 Cycle)
571
Amended
Tc2
Tc3
Tc4
Tnop
Tc1
tAD1
tAD1
tAD1
tAD1
tAD1
CKIO
A25 to A0
Column
address
Column
address
Column
address
Column
address



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