HD6417618 datasheet(637/646 Pages) RENESAS

637 / 646 page

Rev. 6.00 Jun. 12, 2007 Page 605 of 610

REJ09B0131-0600

Index

Access wait control................................. 150

Accessing MII registers .......................... 252

Address array............................................ 58

Address error exception handling ............. 71

Address error sources ............................... 71

Address multiplexing.............................. 154

Addressing modes..................................... 28

Arithmetic operation instructions ............. 41

Asynchronous Mode............................... 362

Auto-refreshing....................................... 174

Bank active ............................................. 167

Basic timing............................................ 146

Basic timing for I/O card interface ......... 187

Basic timing for memory card interface . 185

Bit rate .................................................... 346

Boundary scan ........................................ 507

Branch instructions ................................... 44

Burst read................................................ 161

Burst write .............................................. 165

Bus state controller (BSC) ...................... 105

Byte-selection SRAM interface .............. 179

Cache ........................................................ 49

Cache structure ......................................... 49

Cases when exceptions are accepted......... 76

Changing clock operating mode ............. 203

Changing division ratio........................... 203

Changing frequency................................ 202

Changing multiplication ratio ................. 202

Clock operating modes ........................... 196

Clock Pulse Generator (CPG)................. 193

Coherency of cache and external

memory ..................................................... 57

Compare match timer (CMT) ................. 315

Connection to PHY-LSI.......................... 257

Control registers........................................ 21

CPU........................................................... 19

Data array.................................................. 59

Data register............................................ 457

Data transfer instructions .......................... 39

Divided areas and cache............................ 51

Endian/access size and data alignment ... 141

EtherC receiver ....................................... 249

EtherC transmitter................................... 247

Ethernet controller (EtherC).................... 227

Ethernet controller direct memory

access controller (E-DMAC) .................. 259

Exception handling ................................... 65

Exception handling operations.................. 66

Exception handling vector table................ 67

Extension of chip select (

CSn)

assertion period ....................................... 152

Features of instructions ............................. 25

Flow control............................................ 256

General illegal instructions ....................... 75

General registers (Rn) ............................... 21

HD6417618 Datasheet(PDF) 637 Page - Renesas Technology Corp

HD6417618 Datasheet(HTML) 637 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL