HD6417618 datasheet(539/646 Pages) RENESAS

539 / 646 page

Section 19 User Debugging Interface (H-UDI)

Rev. 6.00 Jun. 12, 2007 Page 507 of 610

REJ09B0131-0600

19.5

Boundary Scan

A command can be set in SDIR by the H-UDI to place the H-UDI pins in boundary scan mode

stipulated by JTAG.

19.5.1

Supported Instructions

This LSI supports the three mandatory instructions defined in the JTAG standard (BYPASS,

SAMPLE/PRELOAD, and EXTEST) and three option instructions (IDCODE, CLAMP, and

HIGHZ).

BYPASS: The BYPASS instruction is a mandatory instruction that operates the bypass register.

This instruction shortens the shift path to speed up serial data transfer involving other chips on the

printed circuit board. While this instruction is executing, the test circuit has no effect on the

system circuits. The upper four bits of the instruction code are 1111.

SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs data from this LSI's internal

circuitry to the boundary scan register, outputs data from the scan path, and loads data onto the

scan path. While this instruction is executed, signals input to this LSI pins are transmitted directly

to the internal circuitry, and internal circuit outputs are directly output externally from the output

pins. This LSI's system circuits are not affected by execution of this instruction. The upper four

bits of the instruction code are 0100.

In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal

circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the

boundary scan register and read from the scan path. Snapshot latching is performed in

synchronization with the rising edge of the TCK signal in the Capture-DR state. Snapshot latching

does not affect normal operation of this LSI.

In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan

when the EXTEST instruction was executed an undefined value would be output from the output

pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST

instruction, the parallel output latch value is constantly output to the output pin).

EXTEST: This instruction is provided to test external circuitry when this LSI is mounted on a

printed circuit board. When this instruction is executed, output pins are used to output test data

(previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the

printed circuit board, and input pins are used to latch test results into the boundary scan register

from the printed circuit board. If testing is carried out by using the EXTEST instruction N times,

the Nth test data is scanned-in when test data (N-1) is scanned out.

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