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HD6417618 Datasheet(PDF) 538 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 538 Page - Renesas Technology Corp

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Section 19 User Debugging Interface (H-UDI)
Rev. 6.00 Jun. 12, 2007 Page 506 of 610
REJ09B0131-0600
TDO
(when the H-UDI
command is set)
TCK
TDO
(when the JTAG
command is set)
tTDO
tTDO
Figure 19.3 H-UDI Data Transfer Timing
19.4.4
H-UDI Reset
An H-UDI reset is generated by setting the H-UDI reset assert command in SDIR. An H-UDI reset
is of the same kind as a power-on reset. An H-UDI reset is released by inputting the H-UDI reset
negate command. The required time between the H-UDI reset assert command and H-UDI reset
negate command is the same as time for keeping the
RESETP pin low to apply a power-on reset.
H-UDI reset assert
H-UDI reset negate
SDIR
LSI internal reset
CPU state
Branch to H'A0000000
Figure 19.4 H-UDI Reset
19.4.5
H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting an H-UDI command in SDIR. An
H-UDI interrupt is an interrupt of general exceptions, resulting in a branch to an address based on
the VBR value plus offset, and with return by the RTE instruction. This interrupt request has a
fixed priority level of 15.
H-UDI interrupts are accepted in sleep mode, but not in standby mode.



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