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HD6417618 Datasheet(PDF) 535 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 535 Page - Renesas Technology Corp |
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535 / 646 page ![]() Section 19 User Debugging Interface (H-UDI) Rev. 6.00 Jun. 12, 2007 Page 503 of 610 REJ09B0131-0600 Bit Pin Name I/O Bit Pin Name I/O 17 PB05/ ICIORD Control 7 PA19/A19 Control 16 PB06/ ICIOWR Control 6 PA20/A20 Control 15 PB01/ IOIS16 Control 5 PA21/A21 Control 14 PB09/ CE2A Control 4 PA22/A22 Control 13 PB10/ CS5B,CE1A Control 3 PA23/A23 Control 12 PB07/ CE2B Control 2 PA24/A24 Control 11 PB08/ CS6B,CE1B Control 1 PA25/A25 Control 10 PA16/A16 Control 0 PD07/IRQ7/SCK2/- Control 9 PA17/A17 Control To TDO 8 PA18/A18 Control Note: * Control means a low active signal. The corresponding pin is driven with an OUT value when the Control is driven low. 19.3.4 ID Register (SDID) SDID is a 32-bit read-only register in which SDIDH and SDIDL are connected. Each register is a 16-bit that can be read by the CPU. To read this register by the H-UDI side, the contents can be read via the TDO pin when the IDCODE command is set and the TAP state is Shift-DR. Writing is disabled. Bit Bit Name Initial Value R/W Description 31 to 0 DID31 to DID0 Refer to description R Device ID 31 to Device ID 0 ID register that is stipulated by JTAG. H'002B200F (initial value) for this LSI. Upper four bits may be changed according to the LSI version. SDIDH corresponds to bits 31 to 16. SDIDL corresponds to bits 15 to 0. |
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