HD6417618 datasheet(425/646 Pages) RENESAS

425 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 393 of 610

REJ09B0131-0600

15.2

Input/Output Pins

Table 15.1 shows the HIF pin configuration.

Table 15.1

Pin Configuration

Name

Abbreviation

I/O

Description

HIF data pins

HIFD15 to HIFD00

I/O

Address, data, or command input/output to the

HIF

HIF chip select

HIFCS

Input

Chip select input to the HIF

HIF register select

HIFRS

Input

Switching between HIF access types

0: Normal access (other than below)

1: Index register write or status register read

HIF write

HIFWR

Input

Write strobe signal. Low level is input when an

external device writes data to the HIF.

HIF read

HIFRD

Input

Read strobe signal. Low level is input when an

external device reads data from the HIF.

HIF interrupt

HIFINT

Output

Interrupt request to an external device from

the HIF

HIF mode

HIFMD

Input

Selects whether or not this LSI is started up in

HIF boot mode. If a power-on reset is

canceled when high level is input, this LSI is

started up in HIF boot mode.

HIFDMAC transfer

request

HIFDREQ

Output

To an external device, DMAC transfer request

with HIFRAM as the destination

HIF boot ready

HIFRDY

Output

Indicates that the HIF reset is canceled in this

LSI and access from an external device to the

HIF can be accepted.

After 10 clock cycles (max.) of the peripheral

clock following negate of the reset input pin of

this LSI, this pin is asserted.

HIF pin enable

HIFEBL

Input

All HIF pins other than this pin are asserted by

high-level input.

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