HD6417618 datasheet(349/646 Pages) RENESAS

Part #	HD6417618

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 13 Compare Match Timer (CMT)

Rev. 6.00 Jun. 12, 2007 Page 317 of 610

REJ09B0131-0600

13.2.2

Compare Match Timer Control/Status Register (CMCSR)

CMCSR is a 16-bit register that indicates compare match generation, enables interrupts and selects

the counter input clock.

CMCSR is initialized to H'0000 by a power-on reset and a transition to standby mode.

Bit

Bit Name

Initial

value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CMF

R/(W)* Compare Match Flag

Indicates whether or not the values of CMCNT and

CMCOR match.

0: CMCNT and CMCOR values do not match

[Clearing condition]

When 0 is written to this bit

1: CMCNT and CMCOR values match

CMIE

R/W

Compare Match Interrupt Enable

Enables or disables compare match interrupt (CMI)

generation when CMCNT and CMCOR values match

(CMF=1).

0: Compare match interrupt (CMI) disabled

1: Compare match interrupt (CMI) enabled

5 to 2



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

HD6417618 Datasheet(PDF) 349 Page - Renesas Technology Corp

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