HD6417618 datasheet(348/646 Pages) RENESAS

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Section 13 Compare Match Timer (CMT)

Rev. 6.00 Jun. 12, 2007 Page 316 of 610

REJ09B0131-0600

13.2

The CMT has the following registers.

• Compare match timer start register (CMSTR)

• Compare match timer control/status register_0 (CMCSR_0)

• Compare match counter_0 (CMCNT_0)

• Compare match constant register_0 (CMCOR_0)

• Compare match timer start register_1 (CMSTR_1)

• Compare match timer control/status register_1 (CMCSR_1)

• Compare match counter_1 (CMCNT_1)

• Compare match constant register_1 (CMCOR_1)

13.2.1

Compare Match Timer Start Register (CMSTR)

CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is

stopped.

CMSTR is initialized to H'0000 by a power-on reset and a transition to standby mode.

Bit

Bit Name

Initial

value

R/W

Description

15 to 2



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

STR1

R/W

Count Start 1

Specifies whether compare match counter 1 operates

or is stopped.

0: CMCNT_1 count is stopped

1: CMCNT_1 count is started

STR0

R/W

Count Start 0

Specifies whether compare match counter 0 operates

or is stopped.

0: CMCNT_0 count is stopped

1: CMCNT_0 count is started

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