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CY8C3865LTI-059 Datasheet(PDF) 107 Page - Cypress Semiconductor |
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CY8C3865LTI-059 Datasheet(HTML) 107 Page - Cypress Semiconductor |
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107 / 129 page ![]() PSoC® 3: CY8C38 Family Data Sheet Document Number: 001-11729 Rev. *R Page 107 of 129 Figure 11-69. Synchronous Read Cycle Timing EM_Addr EM_CEn EM_OEn EM_Data EM_ Clock Address EM_ ADSCn Tcp/2 Tceld Taddrv Tcehd Taddriv Toehd Toeld Tds Tadscld Tadschd Data Note 47. Limited by GPIO output frequency, see Table 11-10 on page 74. Table 11-68. Synchronous Read Cycle Specifications Parameter Description Conditions Min Typ Max Units T EMIF clock period[47] Vdda ≥ 3.3 V 30.3 – – nS Tcp/2 EM_Clock pulse high T/2 – – nS Tceld EM_CEn low to EM_Clock high 5 – – nS Tcehd EM_Clock high to EM_CEn high T/2 – 5 – – nS Taddrv EM_Addr valid to EM_Clock high 5 – – nS Taddriv EM_Clock high to EM_Addr invalid T/2 – 5 – – nS Toeld EM_OEn low to EM_Clock high 5 – – nS Toehd EM_Clock high to EM_OEn high T – – nS Tds Data valid before EM_OEn high T + 15 – – nS Tadscld EM_ADSCn low to EM_Clock high 5 – – nS Tadschd EM_Clock high to EM_ADSCn high T/2 – 5 – – nS [+] Feedback |
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