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CY8C3865LTI-059 Datasheet(PDF) 108 Page - Cypress Semiconductor |
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CY8C3865LTI-059 Datasheet(HTML) 108 Page - Cypress Semiconductor |
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108 / 129 page ![]() PSoC® 3: CY8C38 Family Data Sheet Document Number: 001-11729 Rev. *R Page 108 of 129 Figure 11-70. Synchronous Write Cycle Timing EM_ Addr EM_CEn EM_ WEn EM_ Data EM_ Clock Address EM_ ADSCn Tcp/2 Tceld Taddrv Tcehd Taddriv Twehd Tweld Tds Data Tadscld Tadschd Tdh Note 48. Limited by GPIO output frequency, see Table 11-10 on page 74. Table 11-69. Synchronous Write Cycle Specifications Parameter Description Conditions Min Typ Max Units T EMIF clock Period[48] Vdda ≥ 3.3 V 30.3 – – nS Tcp/2 EM_Clock pulse high T/2 – – nS Tceld EM_CEn low to EM_Clock high 5 – – nS Tcehd EM_Clock high to EM_CEn high T/2 – 5 – – nS Taddrv EM_Addr valid to EM_Clock high 5 – – nS Taddriv EM_Clock high to EM_Addr invalid T/2 – 5 – – nS Tweld EM_WEn low to EM_Clock high 5 – – nS Twehd EM_Clock high to EM_WEn high T/2 – 5 – – nS Tds Data valid before EM_Clock high 5 – – nS Tdh Data invalid after EM_Clock high T – – nS Tadscld EM_ADSCn low to EM_Clock high 5 – – nS Tadschd EM_Clock high to EM_ADSCn high T/2 – 5 – – nS [+] Feedback |
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