CY8C3865LTI-059 datasheet(17/129 Pages) CYPRESS

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PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 17 of 129

4.4.4.2 Auto Repeat DMA

Auto repeat DMA is typically used when a static pattern is

repetitively read from system memory and written to a peripheral.

This is done with a single TD that chains to itself.

4.4.4.3 Ping Pong DMA

A ping pong DMA case uses double buffering to allow one buffer

to be filled by one client while another client is consuming the

data previously received in the other buffer. In its simplest form,

this is done by chaining two TDs together so that each TD calls

the opposite TD when complete.

4.4.4.4 Circular DMA

Circular DMA is similar to ping pong DMA except it contains more

than two buffers. In this case there are multiple TDs; after the last

TD is complete it chains back to the first TD.

4.4.4.5 Scatter Gather DMA

In the case of scatter gather DMA, there are multiple

noncontiguous sources or destinations that are required to

effectively carry out an overall DMA transaction. For example, a

packet may need to be transmitted off of the device and the

packet elements, including the header, payload, and trailer, exist

in various noncontiguous locations in memory. Scatter gather

DMA allows the segments to be concatenated together by using

multiple TDs in a chain. The chain gathers the data from the

multiple locations. A similar concept applies for the reception of

data onto the device. Certain parts of the received data may need

to be scattered to various locations in memory for software

processing convenience. Each TD in the chain specifies the

location for each discrete element in the chain.

4.4.4.6 Packet Queuing DMA

Packet queuing DMA is similar to scatter gather DMA but

specifically refers to packet protocols. With these protocols,

there may be separate configuration, data, and status phases

associated with sending or receiving a packet.

For instance, to transmit a packet, a memory mapped

configuration register can be written inside a peripheral,

specifying the overall length of the ensuing data phase. The CPU

can set up this configuration information anywhere in system

memory and copy it with a simple TD to the peripheral. After the

configuration phase, a data phase TD (or a series of data phase

TDs) can begin (potentially using scatter gather). When the data

phase TD(s) finish, a status phase TD can be invoked that reads

some memory mapped status information from the peripheral

and copies it to a location in system memory specified by the

CPU for later inspection. Multiple sets of configuration, data, and

status phase ‘subchains’ can be strung together to create larger

chains that transmit multiple packets in this way. A similar

concept exists in the opposite direction to receive the packets.

4.4.4.7 Nested DMA

One TD may modify another TD, as the TD configuration space

is memory mapped similar to any other peripheral. For example,

a first TD loads a second TD’s configuration and then calls the

second TD. The second TD moves data as required by the

application. When complete, the second TD calls the first TD,

which again updates the second TD’s configuration. This

process repeats as often as necessary.

4.5 Interrupt Controller

The interrupt controller provides a mechanism for hardware

resources to change program execution to a new address,

independent of the current task being executed by the main

code. The interrupt controller provides enhanced features not

found on original 8051 interrupt controllers:

Thirty-two interrupt vectors

Jumps directly to ISR anywhere in code space with dynamic

vector addresses

Multiple sources for each vector

Flexible interrupt to vector matching

Each interrupt vector is independently enabled or disabled

Each interrupt can be dynamically assigned one of eight

priorities

Eight level nestable interrupts

Multiple I/O interrupt vectors

Software can send interrupts

Software can clear pending interrupts

Figure 4-2 on page 18 represents typical flow of events when an

interrupt triggered. Figure 4-3 on page 19 shows the interrupt

structure and priority polling.

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