CY8C3865LTI-059 datasheet(7/129 Pages) CYPRESS

7 / 129 page

PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 7 of 129

Figure 2-3. 68-pin QFN Part Pinout[9]

Notes

9. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

10. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

(GPIO) P2[6]

(GPIO) P2[7]

(I2C0: SCL, SIO) P12[4]

(I2C0: SDA, SIO) P12[5]

Vssb

Ind

Vboost

Vbat

Vssd

XRES

(TMS, SWDIO, GPIO) P1[0]

(TCK, SWDCK, GPIO) P1[1]

(configurable XRES, GPIO) P1[2]

(TDO, SWV, GPIO) P1[3]

(TDI, GPIO) P1[4]

(nTRST, GPIO) P1[5]

Vddio1

P0[3] (GPIO, OpAmp0-/Extref0)

P0[2] (GPIO, OpAmp0+)

P0[1] (GPIO, OpAmp0out)

P0[0] (GPIO, OpAmp2out)

P12[3] (SIO)

P12[2] (SIO)

Vssd

Vdda

Vssa

Vcca

P15[3] (GPIO, kHz XTAL: Xi)

P15[2] (GPIO, kHz XTAL: Xo)

P12[1] (SIO, I2C1: SDA)

P12[0] (SIO, 12C1: SCL)

P3[7] (GPIO, OpAmp3out)

P3[6] (GPIO, OpAmp1out)

Vddio3

QFN

(Top View)

Lines show Vddio

to I/O supply

association

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