CY8C3865LTI-059 datasheet(25/129 Pages) CYPRESS

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PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 25 of 129

INC DPTR

MOV DPTR, #data16

The extended data pointer SFRs, DPX0, DPX1, MXAX, and

P2AX, hold the most significant parts of memory addresses

during access to the xdata space. These SFRs are used only

with the MOVX instructions.

During a MOVX instruction using the DPTR0/DPTR1 register,

the most significant byte of the address is always equal to the

contents of DPX0/DPX1.

During a MOVX instruction using the R0 or R1 register, the most

significant byte of the address is always equal to the contents of

MXAX, and the next most significant byte is always equal to the

contents of P2AX.

I/O Port SFRs

The I/O ports provide digital input sensing, output drive, pin

interrupts, connectivity for analog inputs and outputs, LCD, and

access to peripherals through the DSI. Full information on I/O

ports is found in I/O System and Routing on page 33.

I/O ports are linked to the CPU through the PHUB and are also

available in the SFRs. Using the SFRs allows faster access to a

limited set of I/O port registers, while using the PHUB allows boot

configuration and access to all I/O port registers.

Each SFR supported I/O port provides three SFRs:

SFRPRTxDR sets the output data state of the port (where × is

port number and includes ports 0–6, 12 and 15).

The SFRPRTxSEL selects whether the PHUB PRTxDR

within the port. If a SFRPRTxSEL[y] bit is high, the

corresponding SFRPRTxDR[y] bit sets the output state for that

pin. If a SFRPRTxSEL[y] bit is low, the corresponding

PRTxDR[y] bit sets the output state of the pin (where y varies

from 0 to 7).

The SFRPRTxPS is a read only register that contains pin state

values of the port pins.

5.7.3.1 xdata Space

The 8051 xdata space is 24-bit, or 16 MB in size. The majority of

this space is not ‘external’—it is used by on-chip components.

See Table 5-5. External, that is, off-chip, memory can be

accessed using the EMIF. See External Memory Interface on

page 23.

Table 5-5. XDATA Data Address Map

Address Range

Purpose

0×00 0000 – 0×00 1FFF

SRAM

0×00 4000 – 0×00 42FF

Clocking, PLLs, and oscillators

0×00 4300 – 0×00 43FF

Power management

0×00 4400 – 0×00 44FF

Interrupt controller

0×00 4500 – 0×00 45FF

Ports interrupt control

0×00 4700 – 0×00 47FF

Flash programming interface

0×00 4900 – 0×00 49FF

I2C controller

0×00 4E00 – 0×00 4EFF

Decimator

0×00 4F00 – 0×00 4FFF

Fixed timer/counter/PWMs

0×00 5000 – 0×00 51FF

I/O ports control

0×00 5400 – 0×00 54FF

EMIF control registers

0×00 5800 – 0×00 5FFF

Analog subsystem interface

0×00 6000 – 0×00 60FF

USB controller

0×00 6400 – 0×00 6FFF

UDB configuration

0×00 7000 – 0×00 7FFF

PHUB configuration

0×00 8000 – 0×00 8FFF

EEPROM

0×00 A000 – 0×00 A400

CAN

0×00 C000 – 0×00 C800

DFB

0×01 0000 – 0×01 FFFF

Digital Interconnect

configuration

0×05 0220 – 0×05 02F0

Debug controller

0×08 0000 – 0×08 1FFF

Flash ECC bytes

0×80 0000 – 0×FF FFFF

External memory interface

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