CY8C3865LTI-059 datasheet(16/129 Pages) CYPRESS

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PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 16 of 129

4.4.2 DMA Features

24 DMA channels

Each channel has one or more transaction descriptors (TD) to

configure channel behavior. Up to 128 total TDs can be defined

TDs can be dynamically updated

Eight levels of priority per channel

Any digitally routable signal, the CPU, or another DMA channel,

can trigger a transaction

Each channel can generate up to two interrupts per transfer

Transactions can be stalled or canceled

Supports transaction size of infinite or 1 to 64 KB

TDs may be nested and/or chained for complex transactions

4.4.3 Priority Levels

The CPU always has higher priority than the DMA controller

when their accesses require the same bus resources. Due to the

system architecture, the CPU can never starve the DMA. DMA

channels of higher priority (lower priority number) may interrupt

current DMA transfers. In the case of an interrupt, the current

transfer is allowed to complete its current transaction. To ensure

latency limits when multiple DMA accesses are requested

simultaneously, a fairness algorithm guarantees an interleaved

minimum percentage of bus bandwidth for priority levels 2

through 7. Priority levels 0 and 1 do not take part in the fairness

algorithm and may use 100 percent of the bus bandwidth. If a tie

occurs on two DMA requests of the same priority level, a simple

round robin method is used to evenly share the allocated

bandwidth. The round robin allocation can be disabled for each

DMA channel, allowing it to always be at the head of the line.

Priority levels 2 to 7 are guaranteed the minimum bus bandwidth

shown in Table 4-7 after the CPU and DMA priority levels 0 and

1 have satisfied their requirements.

When the fairness algorithm is disabled, DMA access is granted

based solely on the priority level; no bus bandwidth guarantees

are made.

4.4.4 Transaction Modes Supported

The flexible configuration of each DMA channel and the ability to

chain multiple channels allow the creation of both simple and

complex use cases. General use cases include, but are not

limited to:

4.4.4.1 Simple DMA

In a simple DMA case, a single TD transfers data between a

source and sink (peripherals or memory location). The basic

timing diagrams of DMA read and write cycles are shown in

Figure 4-1. For more description on other transfer modes, refer

to the Technical Reference Manual.

Figure 4-1. DMA Timing Diagram

Table 4-7. Priority Levels

Priority Level

% Bus Bandwidth

100.0

50.0

25.0

12.5

56.2

63.1

71.5

CLK

ADDR 16/32

WRITE

DATA

READY

Basic DMA Read Transfer without wait states

DATA (A)

ADDRESS Phase

DATA Phase

ADDRESS Phase

DATA Phase

CLK

WRITE

DATA

READY

DATA (A)

Basic DMA Write Transfer without wait states

ADDR 16/32

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