CY8C3865LTI-059 datasheet(43/129 Pages) CYPRESS

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PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 43 of 129

The main component blocks of the UDB are:

PLD blocks – There are two small PLDs per UDB. These blocks

take inputs from the routing array and form registered or

combinational sum-of-products logic. PLDs are used to

implement state machines, state bits, and combinational logic

equations. PLD configuration is automatically generated from

graphical primitives.

Datapath module – This 8-bit wide datapath contains structured

logic to implement a dynamically configurable ALU, a variety

of compare configurations and condition generation. This block

also contains input/output FIFOs, which are the primary parallel

data interface between the CPU/DMA system and the UDB.

Status and control module – The primary role of this block is to

provide a way for CPU firmware to interact and synchronize

with UDB operation.

Clock and reset module – This block provides the UDB clocks

and reset selection and control.

7.2.1 PLD Module

The primary purpose of the PLD blocks is to implement logic

expressions, state machines, sequencers, lookup tables, and

decoders. In the simplest use model, consider the PLD blocks as

a standalone resource onto which general purpose RTL is

synthesized and mapped. The more common and efficient use

model is to create digital functions from a combination of PLD

and datapath blocks, where the PLD implements only the

random logic and state portion of the function while the datapath

(ALU) implements the more structured elements.

Figure 7-7. PLD 12C4 Structure

One 12C4 PLD block is shown in Figure 7-7. This PLD has 12

inputs, which feed across eight product terms. Each product term

(AND function) can be from 1 to 12 inputs wide, and in a given

product term, the true (T) or complement (C) of each input can

be selected. The product terms are summed (OR function) to

create the PLD outputs. A sum can be from 1 to 8 product terms

wide. The 'C' in 12C4 indicates that the width of the OR gate (in

this case 8) is constant across all outputs (rather than variable

as in a 22V10 device). This PLA like structure gives maximum

flexibility and insures that all inputs and outputs are permutable

for ease of allocation by the software tools. There are two 12C4

PLDs in each UDB.

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

IN11

TC TC TC T C TC TC TC TC

TTTTTTTT

AND

Array

MC0

MC1

MC2

OUT0

OUT1

OUT2

OUT3

MC3

SELIN

(carry in)

SELOUT

(carry out)

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