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CY8C3865LTI-059 Datasheet(PDF) 60 Page - Cypress Semiconductor |
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CY8C3865LTI-059 Datasheet(HTML) 60 Page - Cypress Semiconductor |
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60 / 129 page ![]() PSoC® 3: CY8C38 Family Data Sheet Document Number: 001-11729 Rev. *R Page 60 of 129 Figure 8-12. DAC Block Diagram 8.9.1 Current DAC The current DAC (IDAC) can be configured for the ranges 0 to 32 µA, 0 to 256 µA, and 0 to 2.048 mA. The IDAC can be configured to source or sink current. 8.9.2 Voltage DAC For the voltage DAC (VDAC), the current DAC output is routed through resistors. The two ranges available for the VDAC are 0 to 1.024 V and 0 to 4.096 V. In voltage mode any load connected to the output of a DAC should be purely capacitive (the output of the VDAC is not buffered). 8.10 Up/Down Mixer In continuous time mode, the SC/CT block components are used to build an up or down mixer. Any mixing application contains an input signal frequency and a local oscillator frequency. The polarity of the clock, Fclk, switches the amplifier between inverting or noninverting gain. The output is the product of the input and the switching function from the local oscillator, with frequency components at the local oscillator plus and minus the signal frequency (Fclk + Fin and Fclk – Fin) and reduced-level frequency components at odd integer multiples of the local oscillator frequency. The local oscillator frequency is provided by the selected clock source for the mixer. Continuous time up and down mixing works for applications with input signals and local oscillator frequencies up to 1 MHz. Figure 8-13. Mixer Configuration 8.11 Sample and Hold The main application for a sample and hold, is to hold a value stable while an ADC is performing a conversion. Some applications require multiple signals to be sampled simultaneously, such as for power calculations (V and I). Figure 8-14. Sample and Hold Topology ( Φ1 and Φ2 are opposite phases of a clock) Reference Source Scaler I source Range 1x , 8x , 64x I sink Range 1x , 8x , 64x R 3R Vout Iout Vref Vout 0 1 Rmix 0 20 k or 40 k Rmix 0 20 k or 40 k sc_clk sc_clk Vin C2 = 1.7 pF C1 = 850 fF V i n V ref V out 1 2 C 1 C 2 2 1 1 2 1 2 1 1 2 2 C3 C4 Vref V ref Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ [+] Feedback |
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