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CY8C3865LTI-059 Datasheet(PDF) 83 Page - Cypress Semiconductor |
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CY8C3865LTI-059 Datasheet(HTML) 83 Page - Cypress Semiconductor |
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83 / 129 page  PSoC® 3: CY8C38 Family Data Sheet Document Number: 001-11729 Rev. *R Page 83 of 129 11.2.2 Delta-sigma ADC Unless otherwise specified, operating conditions are: Operation in continuous sample mode fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits Reference = 1.024 V internal reference bypassed on P3.2 or P0.3 Unless otherwise specified, all charts and graphs show typical values Table 11-20. 20-bit Delta-sigma ADC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution 8 – 20 bits Number of channels, single ended – – No. of GPIO – Number of channels, differential Differential pair is formed using a pair of GPIOs. –– No. of GPIO/2 – Monotonic Yes – – – – Ge Gain error Buffered, buffer gain = 1, Range = ±1.024 V, 16-bit mode, 25 °C –– ±0.2 % Gd Gain drift Buffered, buffer gain = 1, Range = ±1.024 V, 16-bit mode – – 50 ppm/°C Vos Input offset voltage Buffered, 16-bit mode, VDDA = 2.7 V, 25 °C –– ±0.1 mV TCVos Temperature coefficient, input offset voltage Buffer gain = 1, 16-bit, Range = ±1.024 V –– 55 µV/°C Input voltage range, single ended[36] VSSA –VDDA V Input voltage range, differential unbuf- fered[36] VSSA –VDDA V Input voltage range, differential, buffered[36] VSSA –VDDA – 1 V PSRRb Power supply rejection ratio, buffered[36] Buffer gain = 1, 16-bit, Range = ±1.024 V 90 – – dB CMRRb Common mode rejection ratio, buffered[36] Buffer gain = 1, 16 bit, Range = ±1.024 V 85 – – dB INL20 Integral non linearity[36] Range = ±1.024 V, unbuffered – – ±32 LSB DNL20 Differential non linearity[36] Range = ±1.024 V, unbuffered – – ±1 LSB INL16 Integral non linearity[36] Range = ±1.024 V, unbuffered – – ±2 LSB DNL16 Differential non linearity[36] Range = ±1.024 V, unbuffered – – ±1 LSB INL12 Integral non linearity[36] Range = ±1.024 V, unbuffered – – ±1 LSB DNL12 Differential non linearity[36] Range = ±1.024 V, unbuffered – – ±1 LSB INL8 Integral non linearity[36] Range = ±1.024 V, unbuffered – – ±1 LSB DNL8 Differential non linearity[36] Range = ±1.024 V, unbuffered – – ±1 LSB Rin_Buff ADC input resistance Input buffer used 10 – – M Ω Rin_ADC16 ADC input resistance Input buffer bypassed, 16-bit, Range = ±1.024 V –74[37] –k Ω Rin_ADC12 ADC input resistance Input buffer bypassed, 12 bit, Range = ±1.024 V – 148[37] –k Ω Notes 36. Based on device characterization (not production tested). 37. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual. [+] Feedback |
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