CY8C3865LTI-059 datasheet(19/129 Pages) CYPRESS

19 / 129 page

PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 19 of 129

Figure 4-3. Interrupt Structure

When an interrupt is pending, the current instruction is

completed and the program counter is pushed onto the stack.

Code execution then jumps to the program address provided by

the vector. After the ISR is completed, a RETI instruction is

executed and returns execution to the instruction following the

previously interrupted instruction. To do this the RETI instruction

pops the program counter from the stack.

If the same priority level is assigned to two or more interrupts,

the interrupt with the lower vector number is executed first. Each

interrupt vector may choose from three interrupt sources: Fixed

Function, DMA, and UDB. The fixed function interrupts are direct

connections to the most common interrupt sources and provide

the lowest resource cost connection. The DMA interrupt sources

provide direct connections to the two DMA interrupt sources

provided per DMA channel. The third interrupt source for vectors

is from the UDB digital routing array. This allows any digital signal

available to the UDB array to be used as an interrupt source.

Fixed function interrupts and all interrupt sources may be routed

to any interrupt vector using the UDB interrupt source

connections.

Interrupts 0 to 30

from UDBs

Interrupt

routing logic

to select 31

sources

Individual

Enable Disable

bits

Global Enable

disable bit

Interrupt Enable/

Disable, PEND and

POST logic

Interrupts form Fixed

function blocks, DMA and

UDBs

8 Level

Priority

decoder

for all

interrupts

Highest Priority

Lowest Priority

Interrupt Polling logic

IRC

IRA

IRQ

0 to 30

[15:0]

ACTIVE_INT_NUM

INT_VECT_ADDR

Interrupts 0 to 30

from Fixed

Function Blocks

Interrupts 0 to

30 from DMA

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