CY8C3865LTI-059 datasheet(18/129 Pages) CYPRESS

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Document Number: 001-11729 Rev. *R

Page 18 of 129

PSoC® 3: CY8C38 Family

Data Sheet

Figure 4-2. Interrupt Processing Timing Diagram

Notes

1: Interrupt triggered asynchronous to the clock

2: The PEND bit is set on next active clock edge to indicate the interrupt arrival

3: POST bit is set following the PEND bit

4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)

5: ISR address is posted to CPU core for branching

6: CPU acknowledges the interrupt request

7: ISR address is read by CPU for branching

8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core

10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)

11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status

The total interrupt latency (ISR execution)

= POST + PEND + IRQ + IRA + Completing current instruction and branching

= 1+1+1+2+7 cycles

= 12 cycles

The active interrupt ISR

address is posted to core

Interrupt generation and posting to CPU

The active interrupt

number is posted to core

Interrupt request sent to core for processing

Interrupt is posted to ascertain the priority

Pend bit is set on next system clock active edge

Arrival of new Interrupt

CLK

INT_INPUT

PEND

POST

IRQ

ACTIVE_INT_NUM

(#10)

INT_VECT_ADDR

IRA

IRC

0x0010

CPU Response

Int. State

Clear

Completing current instruction and branching to vector address

Complete ISR and return

IRQ cleared after receiving IRA

POST and PEND bits cleared after IRQ is sleared

0x0000

TIME

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