CY8C3865LTI-059 datasheet(26/129 Pages) CYPRESS

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PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 26 of 129

6. System Integration

6.1 Clocking System

The clocking system generates, divides, and distributes clocks

throughout the PSoC system. For the majority of systems, no

external crystal is required. The IMO and PLL together can

generate up to a 66 MHz clock, accurate to ±1 percent over

voltage and temperature. Additional internal and external clock

sources allow each design to optimize accuracy, power, and

cost. All of the system clock sources can be used to generate

other clock frequencies in the 16-bit clock dividers and UDBs for

anything the user wants, for example a UART baud rate

generator.

Clock generation and distribution is automatically configured

through the PSoC Creator IDE graphical interface. This is based

on the complete system’s requirements. It greatly speeds the

design process. PSoC Creator allows you to build clocking

systems with minimal input. You can specify desired clock

frequencies and accuracies, and the software locates or builds a

clock that meets the required specifications. This is possible

because of the programmability inherent PSoC.

Key features of the clocking system include:

Seven general purpose clock sources

3- to 62-MHz IMO, ±1% at 3 MHz

4- to 25-MHz external crystal oscillator (MHzECO)

Clock doubler provides a doubled clock frequency output for

the USB block, see USB Clock Domain on page 28.

DSI signal from an external I/O pin or other logic

24- to 67-MHz fractional PLL sourced from IMO, MHzECO,

or DSI

Clock doubler

1-kHz, 33-kHz, 100-kHz ILO for WDT and sleep timer

32.768-kHz external crystal oscillator (kHzECO) for RTC

IMO has a USB mode that auto locks to the USB bus clock

requiring no external crystal for USB. (USB equipped parts only)

Independently sourced clock in all clock dividers

Eight 16-bit clock dividers for the digital system

Four 16-bit clock dividers for the analog system

Dedicated 16-bit divider for the bus clock

Dedicated 4-bit divider for the CPU clock

Automatic clock configuration in PSoC Creator

Table 6-1. Oscillator Summary

Source

Fmin

Tolerance at Fmin

Fmax

Tolerance at Fmax

Startup Time

IMO

3 MHz

±1% over voltage and temperature 62 MHz ±7%

10 µs max

MHzECO

4 MHz

Crystal dependent

25 MHz Crystal dependent

5 ms typ, max is crystal dependent

DSI

0 MHz

Input dependent

66 MHz Input dependent

Input dependent

PLL

24 MHz Input dependent

67 MHz Input dependent

250 µs max

Doubler

12 MHz Input dependent

48 MHz Input dependent

1 µs max

ILO

1 kHz

–50%, +100%

100 kHz –55%, +100%

15 ms max in lowest power mode

kHzECO

32 kHz

Crystal dependent

32 kHz

Crystal dependent

500 ms typ, max is crystal dependent

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