CY8C3865LTI-059 datasheet(87/129 Pages) CYPRESS

87 / 129 page

PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 87 of 129

Figure 11-37. Delta-sigma ADC DNL vs Output Code, 16-bit,

48 ksps, 25 °C VDDA = 3.3 V

Figure 11-38. Delta-sigma ADC INL vs Output Code, 16-bit,

48 ksps, 25 °C VDDA = 3.3 V

11.2.3 Voltage Reference

11.2.4 Analog Globals

11.2.5 Comparator

Table 11-27. Voltage Reference Specifications

See also ADC external reference specifications in Section 11.2.2.

Parameter

Description

Conditions

Min

Typ

Max

Units

VREF

Precision reference voltage

Initial trimming

1.023

(–0.1%)

1.024

1.025

(+0.1%)

Temperature drift[39]

–

ppm/°C

Long term drift

–

100

–

ppm/Khr

Thermal cycling drift (stability)[39]

–100

–

ppm

Table 11-28. Analog Globals Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Rppag

Resistance pin-to-pin through

analog global[40]

VDDA = 3.0 V

–

939

1461

Rppmuxbus

Resistance pin-to-pin through

analog mux bus[40]

VDDA = 3.0 V

–

721

1135

Notes

39. Based on device characterization (Not production tested).

40. The resistance of the analog global and analog mux bus is high if VDDA ≤ 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog

mux bus under these conditions is not recommended.

41. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.

Table 11-29. Comparator DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

VOS

Input offset voltage in fast mode

Factory trim, Vdda > 2.7 V,

Vin

≥ 0.5 V

–10

Input offset voltage in slow mode

Factory trim, Vin

≥ 0.5 V

–

VOS

Input offset voltage in fast mode[41] Custom trim

–

Input offset voltage in slow mode[41] Custom trim

–

VOS

Input offset voltage in ultra

low-power mode

–±12

–

VHYST

Hysteresis

Hysteresis enable mode

–

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