CY8C3865LTI-059 datasheet(68/129 Pages) CYPRESS

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PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 68 of 129

Figure 11-4. FCPU vs. VDD

Table 11-3. AC Specifications[24]

Parameter

Description

Conditions

Min

Typ

Max

Units

FCPU

CPU frequency

1.71 V

≤ VDDD ≤ 5.5 V

–

67.01

MHz

FBUSCLK

Bus frequency

1.71 V

≤ VDDD ≤ 5.5 V

–

67.01

MHz

Svdd

VDD ramp rate

–

V/ns

TIO_INIT

Time from VDDD/VDDA/VCCD/VCCA

≥ IPOR to I/O ports set to their reset

states

––

µs

TSTARTUP

Time from VDDD/VDDA/VCCD/VCCA

≥ PRES to CPU executing code at

reset vector

VCCA/VDDA = regulated from

VDDA/VDDD, no PLL used, fast IMO

boot mode (48 MHz typ.)

––

µs

VCCA/VCCD = regulated from

VDDA/VDDD, no PLL used, slow

IMO boot mode (12 MHz typ.)

––

µs

TSLEEP

Wakeup from sleep mode –

Application of non-LVD interrupt to

beginning of execution of next CPU

instruction

––

µs

THIBERNATE

Wakeup from hibernate mode –

Application of external interrupt to

beginning of execution of next CPU

instruction

–

100

µs

5.5 V

1.71 V

0.5 V

0 V

1 MHz

10 MHz

67 MHz

3.3 V

Valid Operating Region

Valid Operating Region with SMP

CPU Frequency

Note

24. Based on device characterization (Not production tested).

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