CY8C3865LTI-059 datasheet(111/129 Pages) CYPRESS

111 / 129 page

PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 111 of 129

11.5.5 SWD Interface

Figure 11-72. SWD Interface Timing

11.5.6 SWV Interface

Table 11-76. SWD Interface AC Specifications[51]

Parameter

Description

Conditions

Min

Typ

Max

Units

f_SWDCK

SWDCLK frequency

3.3 V

≤ VDDD ≤ 5V

–

14[52]

MHz

1.71 V

≤ VDDD < 3.3 V

–

7[52]

MHz

1.71 V

≤ VDDD < 3.3 V,

SWD over USBIO pins

––

5.5[52]

MHz

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T/4

–

T_SWDI_hold

SWDIO input hold after SWDCK high

T = 1/f_SWDCK max

T/4

–

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

–

2T/5

T_SWDO_hold SWDIO output hold after SWDCK low

T = 1/f_SWDCK max

T/4

–

SWDIO

(PSoC 3 reading on SWDIO)

SWDCK

T_SWDI_setup

SWDIO

(PSoC 3 writing to SWDIO)

(1/f_SWDCK)

T_SWDI_hold

T_SWDO_valid

T_SWDO_hold

Table 11-77. SWV Interface AC Specifications[51]

Parameter

Description

Conditions

Min

Typ

Max

Units

SWV mode SWV bit rate

–

Mbit

Notes

51. Based on device characterization (Not production tested).

52. f_SWDCK must also be no more than 1/3 CPU clock frequency.

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