Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

Preview PDF HTML

CY8C3865LTI-059 Datasheet(PDF) 115 Page - Cypress Semiconductor

Part # CY8C3865LTI-059
Description  Programmable System-on-Chip (PSoC짰)
PDF  129 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C3865LTI-059 Datasheet(HTML) 115 Page - Cypress Semiconductor

Back Button CY8C3865LTI-059 Datasheet HTML 111Page - Cypress Semiconductor CY8C3865LTI-059 Datasheet HTML 112Page - Cypress Semiconductor CY8C3865LTI-059 Datasheet HTML 113Page - Cypress Semiconductor CY8C3865LTI-059 Datasheet HTML 114Page - Cypress Semiconductor CY8C3865LTI-059 Datasheet HTML 115Page - Cypress Semiconductor CY8C3865LTI-059 Datasheet HTML 116Page - Cypress Semiconductor CY8C3865LTI-059 Datasheet HTML 117Page - Cypress Semiconductor CY8C3865LTI-059 Datasheet HTML 118Page - Cypress Semiconductor CY8C3865LTI-059 Datasheet HTML 119Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 115 / 129 page
background image
PSoC® 3: CY8C38 Family
Data Sheet
Document Number: 001-11729 Rev. *R
Page 115 of 129
11.6.4 External Crystal Oscillator
11.6.5 External Clock Reference
11.6.6 Phase-Locked Loop
Table 11-84. ECO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
F
Crystal frequency range
4
–
25
MHz
Table 11-85. External Clock Reference AC Specifications[58]
Parameter
Description
Conditions
Min
Typ
Max
Units
External frequency range
0
–
33
MHz
Input duty cycle range
Measured at VDDIO/2
30
50
70
%
Input edge rate
VIL to VIH
0.1
–
–
V/ns
Table 11-86. PLL DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
IDD
PLL operating current
In = 3 MHz, Out = 67 MHz
–
400
–
µA
In = 3 MHz, Out = 24 MHz
–
200
–
µA
Table 11-87. PLL AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Fpllin
PLL input frequency[56]
1–
48
MHz
PLL intermediate frequency[57]
Output of prescaler
1
–
3
MHz
Fpllout
PLL output frequency[56]
24
–
67
MHz
Lock time at startup
–
–
250
µs
Jperiod-rms Jitter (rms)[58]
––
250
ps
Notes
56. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
57. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
58. Based on device characterization (Not production tested).
[+] Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link to Datasheet   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com