CY8C3865LTI-059 datasheet(110/129 Pages) CYPRESS

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PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 110 of 129

11.5.3 Interrupt Controller

11.5.4 JTAG Interface

Figure 11-71. JTAG Interface Timing

Table 11-74. Interrupt Controller AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Delay from interrupt signal input to ISR

code execution from ISR code

Includes worse case completion of

longest instruction DIV with 6

cycles

––

Tcy CPU

Table 11-75. JTAG Interface AC Specifications[49]

Parameter

Description

Conditions

Min

Typ

Max

Units

f_TCK

TCK frequency

3.3 V

≤ VDDD ≤ 5V

–

14[50]

MHz

1.71 V

≤ VDDD < 3.3 V

–

7[50]

MHz

T_TDI_setup

TDI setup before TCK high

(T/10) – 5

–

T_TMS_setup

TMS setup before TCK high

T/4

–

T_TDI_hold

TDI, TMS hold after TCK high

T = 1/f_TCK max

T/4

–

T_TDO_valid

TCK low to TDO valid

T = 1/f_TCK max

–

2T/5

T_TDO_hold

TDO hold after TCK high

T = 1/f_TCK max

T/4

–

TDI

TCK

T_TDI_setup

TDO

(1/f_TCK)

T_TDI_hold

T_TDO_valid

T_TDO_hold

TMS

T_TMS_setup T_TMS_hold

Notes

49. Based on device characterization (Not production tested).

50. f_TCK must also be no more than 1/3 CPU clock frequency.

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