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HD6417618 Datasheet(PDF) 330 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 330 Page - Renesas Technology Corp |
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330 / 646 page ![]() Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev. 6.00 Jun. 12, 2007 Page 298 of 610 REJ09B0131-0600 (1) Countermeasure This problem does not occur with all of the bits in EESR. The description applies to some bits but not others. Table 12.1 shows whether the problem can occur with the individual bits and whether the state of the individual interrupt source is reflected in the descriptor. Table 12.1 EESR Bits for which This Problem can Occur and Reflection of Interrupt Sources in the Descriptor Bit Bit Name Status Possibility of Problem Reflection in Descriptor Interrupt Source 31 Reserved 30 TWB Write-back complete Yes Transmit 29 Reserved 28 Reserved 27 Reserved 26 TABT Transmit abort detected Yes Reflected in TD0 bit8 (TFS8) Transmit 25 RABT Receive abort detected No Reflected in RD0 bit8 (RFS8) Reception 24 RFCOF Receive frame counter overflow Yes Reception 23 ADE Address error No Others 22 ECI EtherC status register interrupt source No Others 21 TC Frame transmission complete Yes Reflected in TD0 bit31 (TACT) Transmit 20 TDE Transmit descriptor empty No Transmit 19 TFUF Transmit FIFO underflow Yes Transmit 18 FR Frame received No Reflected in RD0 bit31 (RACT) Reception 17 RDE Receive descriptor empty No Reception 16 RFOF Receive FIFO overflow Yes Reflected in RD0 bit9 (RFS9) Reception |
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