HD6417618 datasheet(332/646 Pages) RENESAS

332 / 646 page

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 300 of 610

REJ09B0131-0600

Bit

Bit Name Status

Possibility

of Problem

Reflection in

Descriptor

Interrupt

Source

CERF

CRC error in received frame

Reflected in

RD0 bit0

(RFS0)

Reception

"Yes": Setting of this interrupt source bit can fail.

"No":

Setting of this interrupt source bit does not fail.

Take the following countermeasures for bits where the problem can arise.

• Bit 30 (TWB): Write-back complete interrupt source bit in EESR may not be set.

Check the TACT bit in the transmit descriptor. TACT = 0 indicates that the transmission is

complete.

• Bit 26 (TABT): Transmit abort detection interrupt source bit in EESR may not be set.

Since the state of the interrupt source is written back to the relevant descriptor, check the

transmit descriptor (TD0) to confirm the error status.

• Bit 24 (RFCOF): Receive frame counter overflow interrupt source bit in EESR may not be set.

However, even if the software is not notified of the interrupt despite the frame counter having

overflowed, the upper layer (e.g. TCP/IP) can recognize the error because this LSI discards the

frame. After departure from the overflow state, storage in the receive FIFO proceeds normally

from the head of the next frame. Therefore, no problem with the system arises.

• Bit 21 (TC): Frame transmission complete interrupt source bit in EESR may not be set.

For transmission-related processing, either procedure (a) or (b) given below is effective.

(a) Transmission processing without interrupt handling of the frame transmission complete

interrupt

1. Prepare multiple transmit descriptors so that multiple frames can be transmitted.

After setting the transmit descriptors, set bit 0 (TR) in the E-DMAC transmit request

Before setting the next frame for transmission in the descriptor (when a transmission

task arises), check the TACT bit of the corresponding transmit descriptor.

If the TACT bit is clear, set the frame for transmission in the corresponding transmit

descriptor and set the TR bit in EDTRR to start transmission. If the TACT bit is set to

1, do not set the transmit descriptor until the next timing.

(b) For systems where completion of the transmission of each frame must be confirmed (that

is, set frame for transmission

→ initiate transmission → complete frame transmission →

set the next frame for transmission

→ …)

1. Check the TACT bit in the last descriptor of the frame for transmission and confirm

that TACT = 0, which means that the transmission was completed.

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