HD6417618 datasheet(329/646 Pages) RENESAS

329 / 646 page

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 297 of 610

REJ09B0131-0600

12.4

Usage Notes

12.4.1

Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR)

When the status bits in EESR of the on-chip E-DMAC of the SH-Ether chip are used as interrupt

sources, setting of the interrupt source may fail if software writes a 1 to the corresponding status

bit in EESR to clear the bit and this coincides with setting of the status interrupt source in EESR

by the EtherC or E-DMAC. Figure 12.8 shows an example of timing in the case where setting of

the interrupt source in EESR has failed.

(a) In this example, both the reception interrupt and transmission interrupt sources of EESR are

used. Firstly, reception interrupt source A from the EtherC or E-DMAC sets bit A in EESR and

an interrupt is generated.

(b) The interrupt handler writes 1 to bit A to clear it.

signal by the EtherC or E-DMAC take place simultaneously, bit A will be cleared but the

status bit for transmission-interrupt source B in EESR might not be set.

Internal clock (I

φ)

Reception interrupt source A

generated by EtherC/E-DMAC

Transmission interrupt source B

generated by EtherC/E-DMAC

: Expected operation

Bit A in EESR

H'00000001

Bit B in EESR

Write access to EESR

by software

Data to be written to EESR

(a)

(b), (c)

(c)

Simultaneous clearing of the bit

by writing of a 1 and generation

of interrupt source B.

Failure to generate transmission

interrupt source B due to

non-setting of bit B.

Bit clearing

by writing a 1

Reception interrupt source A

is set in bit A of EESR.

Only bit A of EESR

is cleared by software.

Figure 12.8 Timing of the Case where Setting of the Interrupt Source Bit in EESR by the E-

DMAC Fails

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