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HD6417618 Datasheet(PDF) 323 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 323 Page - Renesas Technology Corp

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 6.00 Jun. 12, 2007 Page 291 of 610
REJ09B0131-0600
(b)
Receive Descriptor 1 (RD1)
RD1 specifies the receive buffer length (maximum 64 kbytes).
Bit
Bit Name
Initial
value
R/W
Description
31 to 16
RBL
All 0
R/W
Receive Buffer Length
These bits specify the maximum reception byte length
in the corresponding receive buffer.
The transfer byte length must align with a 16-byte
boundary (bits 19 to 16 cleared to 0). The maximum
receive frame length with one frame per buffer is
1,514 bytes, excluding the CRC data. Therefore, for
the receive buffer length specification, a value of
1,520 bytes (H'05F0) that takes account of a 16-byte
boundary is set as the maximum receive frame
length.
15 to 0
RDL
All 0
R/W
Receive Data Length
These bits specify the data length of a receive frame
stored in the receive buffer.
The receive data transferred to the receive buffer
does not include the 4-byte CRC data at the end of
the frame. The receive frame length is reported as the
number of words (valid data bytes) not including this
CRC data.
(c)
Receive Descriptor 2 (RD2)
RD2 specifies the 32-bit receive buffer start address. The receive buffer start address must be
aligned with a longword boundary. However, when SDRAM is connected, it must be aligned with
a 16-byte boundary.
12.3.2
Transmission
When the transmit function is enabled and the transmit request bit (TR) is set in the E-DMAC
transmit request register (EDTRR), the E-DMAC reads the descriptor used last time from the
transmit descriptor list (in the initial state, the descriptor indicated by the transmission descriptor
start address register (TDLAR)). If the setting of the TACT bit in the read descriptor is active, the
E-DMAC reads transmit frame data sequentially from the transmit buffer start address specified
by TD2, and transfers it to the EtherC. The EtherC creates a transmit frame and starts transmission
to the MII. After DMA transfer of data equivalent to the buffer length specified in the descriptor,
the following processing is carried out according to the TFP value.



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