HD6417618 datasheet(324/646 Pages) RENESAS

Part #	HD6417618

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 292 of 610

REJ09B0131-0600

1. TFP

= 00 or 01 (frame continuation):

Descriptor write-back is performed after DMA transfer.

2. TFP

= 01 or 11 (frame end):

Descriptor write-back is performed after completion of frame transmission.

The E-DMAC continues reading descriptors and transmitting frames as long as the setting of the

TACT bit in the read descriptors is "active." When a descriptor with an "inactive" TACT bit is

read, the E-DMAC resets the transmit request bit (TR) in the transmit register and ends transmit

processing (EDTRR).

This LSI + memory

Transmission flowchart

E-DMAC

EtherC

PHY

Transmit FIFO

EtherC/E-DMAC

initialization

Descriptor and

transmit

buffer setting

Transmit directive

Descriptor read

Descriptor write-back

Transmission

completed

Descriptor read

Transmit data transfer

Frame transmission

Transmit data transfer

Figure 12.4 Sample Transmission Flowchart

HD6417618 Datasheet(PDF) 324 Page - Renesas Technology Corp