HD6417618 datasheet(307/646 Pages) RENESAS

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 275 of 610

REJ09B0131-0600

12.2.9

Receive Missed-Frame Counter Register (RMFCR)

RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not

transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive

frames in the FIFO are discarded. The number of frames discarded at this time is counted. When

the value in this register reaches H'FFFF, counting-up is halted. When this register is read, the

counter value is cleared to 0. Write operations to this register have no effect.

Bit

Bit Name

Initial

value

R/W

Description

31 to 16



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

15 to 0

MFC15 to

MFC0

All 0

Missed-Frame Counter

Indicate the number of frames that are discarded and

not transferred to the receive buffer during reception.

12.2.10

Transmit FIFO Threshold Register (TFTR)

TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the

first transmission is started. The actual threshold is 4 times the set value. The EtherC starts

transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified

by this register, when the transmit FIFO is full, or when 1-frame write is executed. When setting

this register, do so in the transmission-halt state.

Bit

Bit Name

Initial

value

R/W

Description

31 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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