HD6417618 datasheet(311/646 Pages) RENESAS

311 / 646 page

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 279 of 610

REJ09B0131-0600

12.2.13

E-DMAC Operation Control Register (EDOCR)

EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC

operation.

Bit

Bit Name

Initial

value

R/W

Description

31 to 4



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

FEC

R/W

FIFO Error Control

Specifies E-DMAC operation when transmit FIFO

underflow or receive FIFO overflow occurs.

0: E-DMAC operation continues when underflow or

overflow occurs

1: E-DMAC operation halts when underflow or

overflow occurs

AEC

R/W

Address Error Control

Indicates detection of an illegal memory address in an

attempted E-DMAC transfer.

0: Illegal memory address not detected (normal

operation)

1: E-DMAC stops its operation due to illegal memory

address detection

Note: To resume the operation, set the E-DMAC

again after software reset by means of the

SWR bit in EDMR.

EDH

R/W

E-DMAC Halted

0: The E-DMAC is operating normally

1: The E-DMAC has been halted by NMI pin

assertion. E-DMAC operation is restarted by

writing 0



Reserved

This bit is always read as 0. The write value should

always be 0.

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