HD6417618 datasheet(305/646 Pages) RENESAS

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 273 of 610

REJ09B0131-0600

12.2.8

Transmit/Receive Status Copy Enable Register (TRSCER)

TRSCER specifies whether or not transmit and receive status information reported by bits in the

EtherC/E-DMAC status register is to be indicated in bits TFS26 to TFS0 and RFS26 to RFS0 in

the corresponding descriptor. Bits in this register correspond to bits 11 to 0 in the EtherC/E-

DMAC status register (EESR). When a bit is cleared to 0, the transmit status (bits 11 to 8 in

EESR) is indicated in bits TFS3 to TFS0 in the transmit descriptor, and the receive status (bits 7

to 0 in EESR) is indicated in bits RFS7 to RFS0 of the receive descriptor. When a bit is set to 1,

the occurrence of the corresponding interrupt is not indicated in the descriptor. After this LSI is

reset, all bits are cleared to 0.

Bit

Bit Name

Initial

value

R/W

Description

31 to 12



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

CNDCE

R/W

CND Bit Copy Directive

0: Indicates the CND bit state in bit TFS3 in the

transmit descriptor

1: Occurrence of the corresponding interrupt is not

indicated in bit TFS3 of the transmit descriptor

DLCCE

R/W

DLC Bit Copy Directive

0: Indicates the DLC bit state in bit TFS2 of the

transmit descriptor

1: Occurrence of the corresponding interrupt is not

indicated in bit TFS2 of the transmit descriptor

CDCE

R/W

CD Bit Copy Directive

0: Indicates the CD bit state in bit TFS1 of the transmit

descriptor

1: Occurrence of the corresponding interrupt is not

indicated in bit TFS1 of the transmit descriptor

TROCE

R/W

TRO Bit Copy Directive

0: Indicates the TRO bit state in bit TFS0 of the receive

descriptor

1: Occurrence of the corresponding interrupt is not

indicated in bit TFS0 of the receive descriptor

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