HD6417618 datasheet(302/646 Pages) RENESAS

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 270 of 610

REJ09B0131-0600

12.2.7

EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)

EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual

bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the

corresponding bit. In the initial state, interrupts are not enabled.

Bit

Bit Name

Initial

value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

TWBIP

R/W

Write-Back Complete Interrupt Permission

0: Write-back complete interrupt is disabled

1: Write-back complete interrupt is enabled

29 to 27



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TABTIP

R/W

Transmit Abort Detection Interrupt Permission

0: Transmit abort detection interrupt is disabled

1: Transmit abort detection interrupt is enabled

RABTIP

R/W

Receive Abort Detection Interrupt Permission

0: Receive abort detection interrupt is disabled

1: Receive abort detection interrupt is enabled

RFCOFIP

R/W

Receive Frame Counter Overflow Interrupt Permission

0: Receive frame counter overflow interrupt is disabled

1: Receive frame counter overflow interrupt is enabled

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