Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

Preview PDF HTML

HD6417618 Datasheet(PDF) 282 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 282 Page - Renesas Technology Corp

Back Button HD6417618 Datasheet HTML 278Page - Renesas Technology Corp HD6417618 Datasheet HTML 279Page - Renesas Technology Corp HD6417618 Datasheet HTML 280Page - Renesas Technology Corp HD6417618 Datasheet HTML 281Page - Renesas Technology Corp HD6417618 Datasheet HTML 282Page - Renesas Technology Corp HD6417618 Datasheet HTML 283Page - Renesas Technology Corp HD6417618 Datasheet HTML 284Page - Renesas Technology Corp HD6417618 Datasheet HTML 285Page - Renesas Technology Corp HD6417618 Datasheet HTML 286Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 282 / 646 page
background image
Section 11 Ethernet Controller (EtherC)
Rev. 6.00 Jun. 12, 2007 Page 250 of 610
REJ09B0131-0600
1. When the receive enable (RE) bit is set, the receiver enters the receive idle state.
2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver
starts receive processing. Discards a frame with an invalid pattern.
3. In normal mode, if the destination address matches the receiver’s own address, or if broadcast
or multicast transmission or promiscuous mode is specified, the receiver starts data reception.
4. Following data reception from the MII, the receiver carries out a CRC check. The result is
indicated as a status bit in the descriptor after the frame data has been written to memory.
Reports an error status in the case of an abnormality.
5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode
register, the receiver prepares to receive the next frame.
11.4.3
MII Frame Timing
Each MII Frame timing is shown in figure 11.4.
TX-CLK
TX-EN
TXD3 to TXD0
TX-ER
CRS
COL
SFD
Preamble
Data
CRC
Figure 11.4 (1) MII Frame Transmit Timing (Normal Transmission)
TX-CLK
TX-EN
TX-ER
CRS
COL
Preamble
JAM
MII_TXD3 to
MII_TXD0
Figure 11.4 (2) MII Frame Transmit Timing (Collision)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link to Datasheet   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com