HD6417618 datasheet(263/646 Pages) RENESAS

263 / 646 page

Section 11 Ethernet Controller (EtherC)

Rev. 6.00 Jun. 12, 2007 Page 231 of 610

REJ09B0131-0600

11.3

The EtherC has the following registers. For details on addresses and access sizes of registers, see

section 20, List of Registers.

MAC Layer Interface Control Register

• EtherC mode register (ECMR)

• EtherC status register (ECSR)

• EtherC interrupt permission register (ECSIPR)

• PHY interface register (PIR)

• MAC address high register (MAHR)

• MAC address low register (MALR)

• Receive frame length register (RFLR)

• PHY status register (PSR)

• Transmit retry over counter register (TROCR)

• Delayed collision detect counter register (CDCR)

• Lost carrier counter register (LCCR)

• Carrier not detect counter register (CNDCR)

• CRC error frame counter register (CEFCR)

• Frame receive error counter register (FRECR)

• Too-short frame receive counter register (TSFRCR)

• Too-long frame receive counter register (TLFRCR)

• Residual-bit frame counter register (RFCR)

• Multicast address frame counter register (MAFCR)

• IPG register (IPGR)

• Automatic PAUSE frame set register (APR)

• Manual PAUSE frame set register (MPR)

• Automatic PAUSE frame retransfer count set register (TPAUSER)

HD6417618 Datasheet(PDF) 263 Page - Renesas Technology Corp