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HD6417618 Datasheet(PDF) 259 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 259 Page - Renesas Technology Corp |
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259 / 646 page ![]() Section 11 Ethernet Controller (EtherC) IFETH01C_000020030900 Rev. 6.00 Jun. 12, 2007 Page 227 of 610 REJ09B0131-0600 Section 11 Ethernet Controller (EtherC) This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3 MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI) complying with this standard enables the Ethernet controller (EtherC) to perform transmission and reception of Ethernet/IEEE802.3 frames. This LSI has one MAC layer interface. The Ethernet controller is connected to the direct memory access controller for Ethernet controller (E-DMAC) inside this LSI, and carries out high-speed data transfer to and from the memory. Figure 11.1 shows a configuration of the EtherC. 11.1 Features • Transmission and reception of Ethernet/IEEE802.3 frames • Supports 10/100 Mbps receive/transfer • Supports full-duplex and half-duplex modes • Conforms to IEEE802.3u standard MII (Media Independent Interface) • Magic Packet detection and Wake-On-LAN (WOL) signal output • Conforms to IEEE802.3x flow control |
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