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HD6417618 Datasheet(PDF) 254 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 254 Page - Renesas Technology Corp |
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254 / 646 page ![]() Section 10 Power-Down Modes Rev. 6.00 Jun. 12, 2007 Page 222 of 610 REJ09B0131-0600 10.4 Sleep Mode 10.4.1 Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to operate in sleep mode and the clock continues to be output to the CKIO pin. 10.4.2 Canceling Sleep Mode Sleep mode is canceled by an interrupt other than a user break (NMI, H-UDI, IRQ, and on-chip peripheral module) or a reset. Canceling with Interrupt: When a user-break, NMI, H-UDI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. When the priority level of an IRQ or on-chip peripheral module interrupt is lower than the interrupt mask level set in the status register (SR) of the CPU, an interrupt request is not accepted preventing sleep mode from being canceled. Canceling with Reset: Sleep mode is canceled by a power-on reset or an H-UDI reset. |
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