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HD6417618 Datasheet(PDF) 252 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 252 Page - Renesas Technology Corp |
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252 / 646 page ![]() Section 10 Power-Down Modes Rev. 6.00 Jun. 12, 2007 Page 220 of 610 REJ09B0131-0600 10.3.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. Bit Bit Name Initial Value R/W Description 7 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 MSTP15 0 R/W Module Stop Bit 15 When this bit is set to 1, the supply of the clock to the CMT is halted. 0: CMT operates 1: Clock supply to CMT halted 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 MSTP13 0 R/W Module Stop Bit 13 When this bit is set to 1, the supply of the clock to the SCIF2 is halted. 0: SCIF2 operates 1: Clock supply to SCIF2 halted 1 MSTP12 0 R/W Module Stop Bit 12 When this bit is set to 1, the supply of the clock to the SCIF1 is halted. 0: SCIF1 operates 1: Clock supply to SCIF1 halted 0 MSTP11 0 R/W Module Stop Bit 11 When this bit is set to 1, the supply of the clock to the SCIF0 is halted. 0: SCIF0 operates 1: Clock supply to SCIF0 halted |
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