HD6417618 datasheet(200/646 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 168 of 610

REJ09B0131-0600

In a write access, when an auto-precharge is performed, a command cannot be issued to the same

bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active

mode is used, READ or WRIT command can be issued successively if the row address is the

same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write.

There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee

that another row address will be accessed within the period in which this value is maintained by

program execution, it is necessary to set auto-refreshing and set the refresh cycle to no more than

the maximum value of tRAS.

A burst read cycle without auto-precharge is shown in figure 7.17, a burst read cycle for the same

row address in figure 7.18, and a burst read cycle for different row addresses in figure 7.19.

Similarly, a single write cycle without auto-precharge is shown in figure 7.20, a single write cycle

for the same row address in figure 7.21, and a single write cycle for different row addresses in

figure 7.21.

In figure 7.18, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that

issues the READ command. The Tnop cycle is inserted to secure two cycles of CAS latency for

the DQMxx signal that specifies which byte data is read from SDRAM. If the CAS latency is

specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency

can be secured even if the DQMxx signal is asserted after the Tc cycle.

When bank active mode is set, if only accesses to the respective banks in the area 3 are considered,

as long as accesses to the same row address continue, the operation starts with the cycle in figure

7.17 or 7.20, followed by repetition of the cycle in figure 7.18 or 7.21. An access to a different

area during this time has no effect. When a different row address is accessed in the bank active

state, the bus cycle shown in figure 7.19 or 7.22 is executed instead of that in figure 7.18 or 7.21.

In bank active mode, too, all banks become inactive after a refresh cycle.

HD6417618 Datasheet(PDF) 200 Page - Renesas Technology Corp