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HD6417618 Datasheet(PDF) 196 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 196 Page - Renesas Technology Corp

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Section 7 Bus State Controller (BSC)
Rev. 6.00 Jun. 12, 2007 Page 164 of 610
REJ09B0131-0600
Single Read: A read access ends in one cycle when data exists in non-cacheable area and the data
bus width is larger than or equal to access size. Since the burst length is set to 1 in synchronous
DRAM burst read/single write mode, only the required data is output. Consequently, no
unnecessary bus cycles are generated even when a cache-through area is accessed.
Figure 7.14 shows the single read basic timing.
A25 to A0
CSn
RD/
WR
RAS
DQMxx
BS
Tap
Tr
Tc1
Tde
Td1
CAS
CKIO
D15 to D0
A11*
Note: * Address pin to be connected to pin A10 of SDRAM.
Figure 7.14 Basic Timing for Single Read (Auto Precharge)



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