HD6417618 datasheet(197/646 Pages) RENESAS

197 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 165 of 610

REJ09B0131-0600

Burst Write: A burst write occurs in the following cases in this LSI.

1. Access size in writing is larger than data bus width.

2. Write-back of the cache

3. 16-byte transfer by E-DMAC (access to non-cacheable area)

This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1

is performed consecutively eight times to write 16-byte consecutive data to the SDRAM that is

connected to a 16-bit data bus. The relationship between the access size and the number of bursts

is shown in table 7.13.

Figure 7.15 shows a timing chart for burst writes. In burst write, the ACTV command is output in

the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA

command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data

is output simultaneously with the write command. After the write command with the

auto-precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by

the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in

the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However,

other CS areas and other banks can be accessed. The number of Trw1 cycles is specified by bits

TRWL1 and TRWL0 in CS3WCR. The number of Tap cycles is specified by bits WTRP1 and

WTRP0 in CS3WCR.

HD6417618 Datasheet(PDF) 197 Page - Renesas Technology Corp