HD6417618 datasheet(129/646 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev. 6.00 Jun. 12, 2007 Page 97 of 610

REJ09B0131-0600

6.4.2

On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral

modules.

Since a different interrupt vector is allocated to each interrupt source, the exception handling

routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can

be allocated to individual on-chip peripheral modules in interrupt priority registers C to E (IPRC

to IPRE). On-chip peripheral module interrupt exception handling sets the interrupt mask level

bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module

interrupt that was accepted.

6.4.3

User Break Interrupt

A user break interrupt has a priority level of 15, and occurs when the break condition set in the

user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are

held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3 to

I0) in the status register (SR) to level 15. For more details on the user break interrupt, see section

18, User Break Controller (UBC).

6.4.4

H-UDI Interrupt

User debugging interface (H-UDI) interrupt has a priority level of 15, and occurs when an H-UDI

interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are held

until accepted. H-UDI exception handling sets the interrupt mask level bits (I3-I0) in the status

Interface (H-UDI).

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