HD6417618 datasheet(128/646 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev. 6.00 Jun. 12, 2007 Page 96 of 610

REJ09B0131-0600

IRQ7 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ7. Use

the IRQ sense select bits (IRQ71S to IRQ 01S and IRQ70S to IRQ00S) in the IRQ control register

(IRQCR) to select the detection mode from low level detection, falling edge detection, rising edge

detection, and both edge detection for each pin. The priority level can be set from 0 to 15 for each

pin using the interrupt priority registers A and B (IPRA and IPRB).

In the case that the low level detection is selected, an interrupt request signal is sent to the INTC

while the IRQ pin is driven low. The interrupt request signal stops to be sent to the INTC when the

IRQ pin becomes high. It is possible to confirm that an interrupt is requested by reading the IRQ

flags (IRQ7F to IRQ0F) in the IRQ status register (IRQSR).

In the case that the edge detection is selected, an interrupt request signal is sent to the INTC when

the following change on the IRQ pin is detected: from high to low in falling edge detection mode,

from low to high in rising edge detection mode, and from low to high or from high to low in both

edge detection mode. The IRQ interrupt request by detecting the change on the pin is held until the

interrupt request is accepted. It is possible to confirm that an IRQ interrupt request has been

detected by reading the IRQ flags (IRQ7F to IRQ0F) in the IRQ status register (IRQSR). An IRQ

interrupt request by detecting the change on the pin can be withdrawn by writing 0 to an IRQ flag

after reading 1.

In the IRQ interrupt exception handling, the interrupt mask bits (I3 to I0) in the status register

(SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block

diagram of the IRQ7 to IRQ0 interrupts.

IRQCR.IRQn1S

IRQCR.IRQn0S

IRQSR.IRQnF

IRQSR.IRQnL

IRQn pins

RESIRQn

Level

detection

Edge

detection

CPU interrupt

request

(Acceptance of IRQn interrupt/

writing 0 after reading IRQnF = 1)

n = 7 to 0

Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control

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