HD6417618 datasheet(103/646 Pages) RENESAS

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Section 5 Exception Handling

Rev. 6.00 Jun. 12, 2007 Page 71 of 610

REJ09B0131-0600

5.3

Address Errors

5.3.1

Address Error Sources

Address errors occur when instructions are fetched or data is read from or written to, as shown in

table 5.6.

Table 5.6

Bus Cycles and Address Errors

Bus Cycle

Type

Bus Master

Bus Cycle Description

Address Errors

CPU

Instruction fetched from even address

None (normal)

Instruction

fetch

Instruction fetched from odd address

Address error occurs

CPU

Word data accessed from even address

None (normal)

Data

read/write

Word data accessed from odd address

Address error occurs

Longword data accessed from a longword

boundary

None (normal)

Longword data accessed from other than a

long-word boundary

Address error occurs

5.3.2

Address Error Exception Source

When an address error exception is generated, the bus cycle which caused the address error ends,

the current instruction finishes, and then the address error exception handling starts. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address

of the instruction which caused an address error exception. When the instruction that caused

the exception is placed in the delay slot, the address of the delayed branch instruction which is

placed immediately before the delay slot.

3. The start address of the exception handling routine is fetched from the exception handling

vector table that corresponds to the generated address error, and the program starts executing

from that address. This branch is not a delayed branch.

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