HD6417618 datasheet(102/646 Pages) RENESAS

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Section 5 Exception Handling

Rev. 6.00 Jun. 12, 2007 Page 70 of 610

REJ09B0131-0600

Power-On Reset by WDT: When TCNT of the WDT overflows while a setting is made so that a

power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the power-

on reset state.

If a reset caused by the signal input on the

RES pin and a reset caused by a WDT overflow occur

simultaneously, the

RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0.

When the power-on reset exception handling caused by the WDT is started, the CPU operates as

follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception handling vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)

of the status register (SR) are set to H'F (B'1111).

4. The values fetched from the exception handling vector table are set in the PC and SP, then the

program starts.

5.2.3

H-UDI Reset

The H-UDI reset is generated by issuing the H-UDI reset assert command. The CPU operation is

described below. For details, see section 19, User Debugging Interface (H-UDI).

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception handling vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)

in the status register (SR) are set to H'F (B'1111).

4. The values fetched from the exception handling vector table are set in PC and SP, then the

program starts.

HD6417618 Datasheet(PDF) 102 Page - Renesas Technology Corp