HD6417618 datasheet(101/646 Pages) RENESAS

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Section 5 Exception Handling

Rev. 6.00 Jun. 12, 2007 Page 69 of 610

REJ09B0131-0600

5.2

Resets

5.2.1

Types of Resets

Resets have priority over any exception source. As table 5.5 shows, a power-on reset initializes all

modules in this LSI.

Table 5.5

Reset Status

Conditions for Transition to

Reset State

Internal State

Type

RES

WDT

Overflow

H-UDI

Command

CPU, INTC

On-Chip

Peripheral

Module

PFC, I/O Port

Low



Initialized

Power-on reset

High

Overflow



Initialized

H-UDI reset

High

Not

overflowed

Reset assert

command

Initialized

5.2.2

Power-On Reset

Power-On Reset by

RES Pin: When the RES pin is driven low, this LSI enters the power-on

reset state. To reliably reset this LSI, the

RES pin should be kept low for at least the oscillation

settling time when applying the power or when in standby mode (when the clock is halted) or at

least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and

all registers of on-chip peripheral modules are initialized.

In the power-on reset state, power-on reset exception handling starts when driving the

RES pin

high after driving the pin low for the given time. The CPU operates as follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception handling vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)

of the status register (SR) are set to H'F (B'1111).

4. The values fetched from the exception handling vector table are set in PC and SP, then the

program starts.

Be certain to always perform power-on reset exception handling when turning the system power

on.

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