HD6417618 datasheet(581/646 Pages) RENESAS

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Section 21 Electrical Characteristics

Rev. 6.00 Jun. 12, 2007 Page 549 of 610

REJ09B0131-0600

21.4.2

Control Signal Timing

Table 21.8

Control Signal Timing

Conditions: V

CCQ = 3.0 V to 3.6 V, VCC = 1.4 V to 1.6 V,

a = –20°C to +75°C (regular specifications),

a = –40°C to +85°C (wide-range specifications)

Item

Symbol

Min.

Max.

Unit

Reference

Figures

RES pulse width

RESW

20*



bcyc*

RES setup time*1

RESS



Figures 21.7 and

21.8

RES hold time

RESH



NMI setup time*

NMIS



Figure 21.8

NMI hold time

NMIH



IRQ7 to IRQ0 setup time*

IRQS



IRQ7 to IRQ0 hold time

IRQH



Bus tri-state delay time 1

BOFF1



Figure 21.9

Bus tri-state delay time 2

BOFF2



Bus buffer on time 1

BON1



Bus buffer on time 2

BON2



Notes: 1. The

RES, NMI, and IRQ7 to IRQ0 signals are asynchronous signals. When the setup

time is satisfied, a signal change is detected at the rising edge of the clock signal. When

the setup time is not satisfied, a signal change may be delayed to the next rising edge.

2. In standby mode, t

RESW = tOSC2 (10 ms). When changing the clock multiplication, tRESW = tPLL1

(100

µs).

3. t

bcyc indicates the period of the external bus clock (Bφ).

CKIO

tRESS

RES

tRESW

Figure 21.7 Reset Input Timing

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