HD6417618 datasheet(577/646 Pages) RENESAS

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Section 21 Electrical Characteristics

Rev. 6.00 Jun. 12, 2007 Page 545 of 610

REJ09B0131-0600

21.4.1

Clock Timing

Table 21.7

Clock Timing

Conditions: V

CCQ = 3.0 V to 3.6 V, VCC = 1.4 V to 1.6 V,

a = –20°C to +75°C (regular specifications),

a = –40°C to +85°C (wide-range specifications),

External bus operating frequency (Max.) = 50 MHz,

Item

Symbol

Min.

Max.

Unit.

Reference Figures

EXTAL clock input frequency

MHz

Figure 21.1

EXTAL clock input cycle time

Excyc

100

EXTAL clock input low pulse

width

EXL



EXTAL clock input high pulse

width

EXH



EXTAL clock rising time

Exr



EXTAL clock falling time

Exf



CKIO clock output frequency

MHz

Figure 21.2

CKIO clock output cycle time

cyc

CKIO clock low pulse width

CKOL



CKIO clock high pulse width

CKOH



CKIO clock rising time

CKOr



CKIO clock falling time

CKOf



CK_PHY clock low pulse width

CKPHYL



CK_PHY clock high pulse width t

CKPHYH



CK_PHY clock rising time

CKPHYr



CK_PHY clock falling time

CKPHYf



Oscillation settling time

(power-on)

OSC1



Figure 21.3

RES setup time

RESS



RES assert time

RESW



bcyc*

Figures 21.3 and 21.4

Oscillation settling time 1

(leaving standby mode)

OSC2



Figure 21.4

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