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HD6417618 Datasheet(PDF) 578 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 578 Page - Renesas Technology Corp |
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578 / 646 page  Section 21 Electrical Characteristics Rev. 6.00 Jun. 12, 2007 Page 546 of 610 REJ09B0131-0600 Item Symbol Min. Max. Unit. Reference Figures Oscillation settling time 2 (leaving standby mode) t OSC3 10 ms Figure 21.5 PLL synchronize settling time t PLL 100 µs Figure 21.6 Note: * t bcyc indicates the period of the external bus clock (Bφ). tEXH tEXf tEXr tEXL tEXcyc VIH VIH VIH 1/2 Vcc 1/2 Vcc VIL VIL Note: * When the clock is input to the EXTAL pin EXTAL* (input) Figure 21.1 External Clock Input Timing tcyc tCKOL tCKOH VOH 1/2 Vcc 1/2 Vcc tCKOr tCKOf VOH VOL VOL VOH CKIO (output) 40 ns tCKPHYL tCKPHYH VOH 1/2 Vcc 1/2 Vcc tCKPHYr tCKPHYf VOH VOL VOL VOH CK_PHY Note: The CK_PHY output timing is the timing when its frequency is set to 25 MHz. Figure 21.2 CKIO and CK_PHY Clock Output Timings |
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